1. Field of the Invention
The present invention relates to a method of forming sidewalls around a gate electrode material of a semiconductor element.
2. Description of the Related Art
U.S. Pat. No. 4,879,254 discloses a fine technique of forming a sidewall at each side of an insulation layer of a semiconductor device by reactive ion etching and forming a transmission path by self-alignment with the insulation layer and sidewall as masks. Japanese Unexamined Patent Publication No. 2-86136 discloses a technique of forming, in a semiconductor device, a sidewall of about 1 .mu.m thick by controlling the thickness of an insulation film to 2 to 3 .mu.m and the side wall angle of a polysilicon gate electrode material to 80 to 90 degrees while minimizing an over-etching quantity.
According to the latter disclosure, the insulation film used for forming the sidewall is very thick at 2 to 3 .mu.m, and the sidewall angle must be restricted to 80 to 90 degrees. The thick insulation film needs a long over-etching time when forming the sidewall, so that it is very difficult to minimize an etching effect of part that must not be etched. Accordingly, this technique has no practical use.